Tutorial: SystemC Design and Verification – Solidifying the Abstraction Above RTL

SystemCPresented at DVCon U.S. 2017 on February 27, 2017

Each year the EDA community makes critical advances in SystemC. As we do, the momentum toward SystemC as the primary point of entry above RTL becomes more tantalizing. Will this be the year your team makes the leap? This tutorial could answer that question for you.

This tutorial focuses on three key components that could help you make that decision: design, modeling, and testbench. We start by examining the latest advances in the SystemC language including the synthesizable subset and CCI configuration. A discussion of modeling for high-performance simulation follows to complete our view of the overall design. Of course, we need to verify this fast-running design with a testbench approach that can be reused at RTL so we’ll discuss how to apply the emerging UVM-SystemC standard.

The tutorial is split into three sections:

  • Part 1: Synthesizable Subset Update
    Peter Frey, Mentor

  • Part 2: SystemC Configuration Tutorial - A Preview of the Draft Standard
    Trevor Wieman, Intel

  • Part 3: UVM-SystemC Standardization Status and Latest Developments
    Trevor Wieman, Intel; Slides by Mike Meredith, Cadence 

View slides >



Thanks to our Sponsors

CadenceMentor, a Siemens BusinessSynopsys