UVM Forums

UVM_ANALYSIS port in sequence

bverma — Fri, 18 May 2012 00:45:46 GMT

Can I declare a uvm_analysis port in sequence ?

I get message like

Error-[ICTTFC] Incompatible complex type usage
/tools/eda/VCS/vF-2011.12/etc/uvm-1.1/tlm1/uvm_analysis_port.svh, 112
Incompatible complex type usage in task or function call.
The following expression is incompatible with the formal parameter of the
function. The type of the actual is 'class ....'

Thanks

Simulation blocked at waiting statement in main_phase

jhpark — Thu, 17 May 2012 01:00:23 GMT

Dear,

I am implementing UVM code for reset test using reset_phase and main_phase with Cadence IES.
My test sequence injects multiple resets during simulation.
Main_phase in agent1 waits for event "posedge top.resetn" and another main_phase in agent2 waits for event "negedge top.resetn".
But two main_phase do not proceed, they are blocked at waiting statement.
What's the problem?

Thanks & Regards,
//JunH Park

P.S. I attached three contents.
1. my code : test.sv
2. run script
3. irun.log file

1. test.sv
--------------------------------------------------------------------------------------------
import uvm_pkg::*;
`include "uvm_macros.svh"

// ------------------------------------------
//
// Agent
//
// ------------------------------------------
class simple_agent1 extends uvm_agent;

int agent_cnt;

`uvm_component_utils(simple_agent1)

function new (string name, uvm_component parent);
super.new(name, parent);
endfunction : new

extern virtual function void build_phase(uvm_phase phase);
extern virtual task reset_phase(uvm_phase phase);
extern virtual task main_phase(uvm_phase phase);

endclass : simple_agent1

function void simple_agent1::build_phase(uvm_phase phase);
super.build();
endfunction

task simple_agent1::reset_phase(uvm_phase phase);
`uvm_info(get_type_name(), $sformatf("-----> reset_phase"), UVM_LOW)
agent_cnt = 1000;
endtask

task simple_agent1::main_phase(uvm_phase phase);
`uvm_info(get_type_name(), $sformatf("main_phase ----->"), UVM_LOW)
@(posedge top.resetn);
`uvm_info(get_type_name(), $sformatf("----- after posedge top.reset"), UVM_LOW)
forever begin
agent_cnt++;
`uvm_info(get_type_name(), $sformatf("main_phase[%0d]", agent_cnt), UVM_LOW)
#10;
end
`uvm_info(get_type_name(), $sformatf("-----> main_phase"), UVM_LOW)
endtask

// ------------------------------------------
//
// Agent2
//
// ------------------------------------------
class simple_agent2 extends uvm_agent;

bit once = 1;

`uvm_component_utils(simple_agent2)

function new (string name, uvm_component parent);
super.new(name, parent);
endfunction : new

extern virtual task reset_phase(uvm_phase phase);
extern virtual task main_phase(uvm_phase phase);

endclass : simple_agent2

task simple_agent2::reset_phase(uvm_phase phase);
`uvm_info(get_type_name(), $sformatf("-----> reset_phase"), UVM_LOW)
endtask

task simple_agent2::main_phase(uvm_phase phase);
`uvm_info(get_type_name(), $sformatf("main_phase ----->"), UVM_LOW)

@(negedge top.resetn);
`uvm_info(get_type_name(), "", UVM_LOW)
`uvm_info(get_type_name(), "", UVM_LOW)
`uvm_info(get_type_name(), "--------------- RESET ---------------", UVM_LOW)
`uvm_info(get_type_name(), "", UVM_LOW)
`uvm_info(get_type_name(), "", UVM_LOW)

`uvm_info(get_type_name(), $sformatf("-----> main_phase"), UVM_LOW)

endtask

// ------------------------------------------
//
// vseqr
//
// ------------------------------------------
class vseqr_c extends uvm_sequencer;

`uvm_component_utils(vseqr_c)

function new (string name, uvm_component parent);
super.new(name, parent);
endfunction : new

endclass : vseqr_c

// ------------------------------------------
//
// TB
//
// ------------------------------------------
class tb_c extends uvm_env;

`uvm_component_utils(tb_c)

vseqr_c vseqr;
simple_agent1 agent;
simple_agent2 agent2;

function new (string name, uvm_component parent);
super.new(name, parent);
endfunction : new

function void build_phase(uvm_phase phase);
super.build();
vseqr = vseqr_c::type_id::create("vseqr", this);
agent = simple_agent1::type_id::create("agent", this);
agent2 = simple_agent2::type_id::create("agent2", this);
endfunction

endclass : tb_c

// ----------------------------------------
//
// Test case
//
// ----------------------------------------
class simple_test extends uvm_test;

bit once = 1;
tb_c tb;
int test_cnt;

`uvm_component_utils(simple_test)

function new(string name, uvm_component parent);
super.new(name, parent);
endfunction : new

function void build_phase(uvm_phase phase);
super.build();
tb = tb_c::type_id::create("tb", this);
uvm_config_db#(uvm_object_wrapper)::set(this, "tb.vseqr.run_phase", "default_sequence", simple_vseq_c::type_id::get());

endfunction

endclass : simple_test

// ------------------------------------------
//
// Verilog top module
//
// ------------------------------------------
module top;

reg resetn;

initial begin
run_test("simple_test");
end

initial begin
$shm_open("test.shm");
$shm_probe("AS");
end

endmodule

// ------------------------------------------
//
// TEST sequence - virtual sequence
//
// ------------------------------------------
class simple_vseq_c extends uvm_sequence;

`uvm_object_utils_begin(simple_vseq_c)
`uvm_object_utils_end

`uvm_declare_p_sequencer(vseqr_c)

function new (string name = "simple_vseq_c");
super.new(name);
endfunction : new

virtual task pre_body();
if (starting_phase != null) begin
`uvm_info(get_type_name(), "objection is raised", UVM_LOW)
starting_phase.raise_objection(this, {"Run sequence '", get_full_name(), "'"});
end
endtask

virtual task body();
`uvm_info(get_type_name(), "Start of body() in vseq", UVM_LOW)

top.resetn = 1;
`uvm_info(get_type_name(), "RESET = 1", UVM_LOW)

// --- 1st RESET
#50
top.resetn = 0;
`uvm_info(get_type_name(), "RESET = 0", UVM_LOW)
#50
top.resetn = 1;
`uvm_info(get_type_name(), "RESET = 1", UVM_LOW)

// --- Operation
#300

// --- 2nd RESET
#50
top.resetn = 0;
`uvm_info(get_type_name(), "RESET = 0", UVM_LOW)
#50
top.resetn = 1;
`uvm_info(get_type_name(), "RESET = 1", UVM_LOW)

// --- Operation
#400

`uvm_info(get_type_name(), "End of body() in vseq", UVM_LOW)

endtask

virtual task post_body();
if (starting_phase != null) begin
`uvm_info(get_type_name(), "objection is dropped", UVM_LOW)
starting_phase.drop_objection(this, {"Run sequence '", get_full_name(), "'"});
end
endtask

endclass : simple_vseq_c

// ------------------------------------------
//
// Define report format
//
// ------------------------------------------
class report_server_c extends uvm_report_server;
static bit initialized = init();

static function bit init();
uvm_report_global_server global_report_server = new;
report_server_c mysrv = new;
global_report_server.set_server(mysrv);
endfunction: init

virtual function string compose_message(uvm_severity severity,
string name,
string id,
string message,
string filename,
int line);
string msg = "";
uvm_severity_type sv;
sv = uvm_severity_type'(severity);
$timeformat(-9, 0, "", 20);
$sformat(msg, "[%0t] %0s (%0s) %0s", $time, sv.name, id, message);
return msg;
endfunction: compose_message
endclass: report_server_c
--------------------------------------------------------------------------------------------------------------

2. run_script
--------------------------------------------------------------------------------------------
#!/bin/csh -f
irun \
test.sv \
-uvmhome /appl/SOL/INCISIV/INCISIV102s029/tools/uvm-1.1 \
+UVM_TIMEOUT=1000000 \
-timescale 1ns/10ps \
+UVM_VERBOSITY=UVM_LOW \
-access +rwc
--------------------------------------------------------------------------------------------

3. irun.log file
--------------------------------------------------------------------------------------------
irun: 10.21-s010: (c) Copyright 1995-2012 Cadence Design Systems, Inc.
TOOL: irun 10.21-s010: Started on May 17, 2012 at 08:45:13 KST
irun
test.sv
-uvmhome /appl/SOL/INCISIV/INCISIV102s029/tools/uvm-1.1
+UVM_TIMEOUT=1000000
-timescale 1ns/10ps
+UVM_VERBOSITY=UVM_LOW
-access +rwc

...

[0] UVM_INFO (RNTST) Running test simple_test...
[0] UVM_INFO (TIMOUTSET) '+UVM_TIMEOUT=1000000' provided on the command line is being applied.
[0] UVM_INFO (simple_vseq_c) objection is raised
[0] UVM_INFO (simple_vseq_c) Start of body() in vseq
[0] UVM_INFO (simple_vseq_c) RESET = 1
[0] UVM_INFO (simple_agent2) -----> reset_phase
[0] UVM_INFO (simple_agent1) -----> reset_phase
[0] UVM_INFO (simple_agent2) main_phase ----->
[0] UVM_INFO (simple_agent1) main_phase ----->
[50] UVM_INFO (simple_vseq_c) RESET = 0
[100] UVM_INFO (simple_vseq_c) RESET = 1
[450] UVM_INFO (simple_vseq_c) RESET = 0
[500] UVM_INFO (simple_vseq_c) RESET = 1
[900] UVM_INFO (simple_vseq_c) End of body() in vseq
[900] UVM_INFO (simple_vseq_c) objection is dropped
[900] UVM_INFO (TEST_DONE) 'run' phase is ready to proceed to the 'extract' phase

--- UVM Report catcher Summary ---

Number of demoted UVM_FATAL reports : 0
Number of demoted UVM_ERROR reports : 0
Number of demoted UVM_WARNING reports: 0
Number of caught UVM_FATAL reports : 0
Number of caught UVM_ERROR reports : 0
Number of caught UVM_WARNING reports : 0

--- UVM Report Summary ---

** Report counts by severity
UVM_INFO : 16
UVM_WARNING : 0
UVM_ERROR : 0
UVM_FATAL : 0
** Report counts by id
[RNTST] 1
[TEST_DONE] 1
[TIMOUTSET] 1
[simple_agent1] 2
[simple_agent2] 2
[simple_vseq_c] 9
Simulation complete via $finish(1) at time 900 NS + 46
/appl/SOL/INCISIV/INCISIV102s029/tools/uvm-1.1/uvm_lib/uvm_sv/sv/base/uvm_root.svh:408 $finish;
ncsim> exit
TOOL: irun 10.21-s010: Exiting on May 17, 2012 at 08:45:21 KST (total: 00:00:08)

Want to Set NO_REG_TESTS in Environment for some registers

akshay.raoy — Wed, 16 May 2012 11:28:07 GMT

Want to set attribute NO_REG_TESTS for few Status resigters, so that when reset sequence will disable reading the register.

I have made

uvm_resource_db#(bit)::set({"REG::",regmodel.debug _status.get_full_name(),".*"},"NO_REG_TESTS",1,thi s);
uvm_resource_db#(bit)::set({"REG::",regmodel.debug _status.get_full_name(),".*"},"NO_REG_HW_RESET_TES T",1,this);

in environment but still i could see debug_status register being tested.
Can anyone give me the solution how to set this attributes.

-Akshay Rao

uvm_comparer and message verbosity issue

klarson — Mon, 14 May 2012 20:55:12 GMT

I'm trying to suppress the default messages that occur when you do a 'compare' of two uvm_object's that don't match. It looks like the standard way to do this would be to create a uvm_comparer object to establish a custom compare policy, but I'm running into problems.

According to the documentation, there is a 'verbosity' variable within the uvm_comparer object with the purpose of setting the message filter level for such messages... perfect! Unfortunately though... it doesn't work :(

Below is the actual code from the print_msg() routine of the uvm_comparer object. In the comments for the function, it describes the desired behavior. However, the implementation seems to be wrong, it disregards the 'verbosity' setting altogether, and hardcodes UVM_LOW as the verbosity level:

Quote:

// Function: print_msg
//
// Causes the error count to be incremented and the message, ~msg~, to be
// appended to the string (a newline is used to separate
// messages).
//
// If the message count is less than the setting, then the message
// is printed to standard-out using the current verbosity and severity
// settings. See the and variables for more information.

function void print_msg (string msg);
result++;
if(result <= show_max) begin
msg = {"Miscompare for ", uvm_object::__m_uvm_status_container.scope.get(), ": ", msg};
uvm_report_info("MISCMP", msg, UVM_LOW);
end
miscompares = { miscompares, uvm_object::__m_uvm_status_container.scope.get(), ": ", msg, "\n" };
endfunction

Has anybody else run into this? This looks like a bug in the UVM library, or am I interpretting the desired behavior incorrectly?

random variable of type bit with varying width

meenu — Sun, 13 May 2012 15:18:42 GMT

Hi
In a register sequence i would like to use data of type uvm_reg_data_t where the value of data should be random.

uvm_reg_data_t data;

size = rg.get_n_bits();
data[size-1:0] = $random;

What should be the type of the variable size? Should it be a parameter or define?
I would like the value of size to change according to the width of the register. So the width of data should change according to the width of the register.

What is the best way to do this?

Locking register blocks and building system-level register blocks.

steveb — Fri, 11 May 2012 15:13:37 GMT

I'm running into an error with my register blocks that works fine for MTI and NCSIM but doesn't work in VCS.
What's the UVM policy on when a lock_model() statement should be called?

I have a system-level testbench where there are unit-level register blocks that get integrated into the top-level register block. In each unit-level build(), I add all the registers then lock_model(). In the system-level register block I build each unit-level register block, add them as submaps, then lock_model().

This seems to make sense to me because each unit-level register block does a lock_model() and that exact code can be re-used at the system-level. However, VCS doesn't like that. It only works for me if the lock_model() is done only at the system-level register block.

Which method is correct? Is it valid to lock unit-level register blocks before locking the top-level register block? I wanted to ask here before filing an issue against VCS.

VCS generates the following error if the unit-level blocks are locked first:
UVM_FATAL @ 0 ns: reporter [REG/MAP/UNMAPD] Address map "unit_regblk" in block "sys_regblk.unit_regblk" is not mapped in an address map in parent block of type "sys_regblk".

A related question to this issue is why does VCS have this piece of code checking to see if a map has a parent map when it's not part of the official UVM-1.1 code?
I've search the UVM git repository and can't seem to find anything related to this UNMAPD check that's in the UVM code distributed with VCS.

Thanks,
Steve

register reset value issue : uvm_resgister_model generated usibg ralgen (synopsys)

ddhiran — Fri, 11 May 2012 09:41:05 GMT

Hello All,

The issue discussed here is regarding the uvm_register_model that was generated using ralgen script by synopsys. After reset, if the register is accessed using hierarchy “ ..value “ always returns “zero” even for registers that were configured with “non_zero” reset value. Because of this the coverage collected on the register is wrong. Has anybody faced this issue? The detailed description of the issue is copied below.

UVM version used is uvm-1.0p1.
VCS version used is Version E-2011.03-3_Full64

Detailed description of issue :
---------------------------------------------------------------
The register class copied below was generated using ralgen script.

Register class description :
------------------------------------------
class register_a extends uvm_reg;
rand uvm_reg_field A1;
rand uvm_reg_field A2;
local uvm_reg_data_t m_current;
local uvm_reg_data_t m_data;
local uvm_reg_data_t m_be;
local bit m_is_read;

covergroup cg_vals ();
option.per_instance = 1;
A1_value : coverpoint A1.value {
bins min = { 16'h0 };
bins max = { 16'hFFFF };
bins others = { [16'h1:16'hFFFE] };
option.weight = 3;
}
A2_value : coverpoint A2.value {
bins min = { 16'h0 };
bins max = { 16'hFFFF };
bins others = { [16'h1:16'hFFFE] };
option.weight = 3;
}
endgroup : cg_vals

function new(string name = "rate_chng_timer");
super.new(name, 32,build_coverage(UVM_CVR_REG_BITS+UVM_CVR_FIELD_V ALS));
if (has_coverage(UVM_CVR_REG_BITS))
cg_bits = new();
if (has_coverage(UVM_CVR_FIELD_VALS))
cg_vals = new();
endfunction: new

virtual function void build();
this.A1 = uvm_reg_field::type_id::create("A1");
this.A1.configure(this, 16, 0, "RW", 0, 16'hd, 1, 0, 1);
this.A2 = uvm_reg_field::type_id::create("A2");
this.A2.configure(this, 16, 16, "RW", 0, 16'hd, 1, 0, 1);
endfunction: build

`uvm_object_utils(register_a)

virtual function void sample(uvm_reg_data_t data,
uvm_reg_data_t byte_en,
bit is_read,
uvm_reg_map map);
if (get_coverage(UVM_CVR_REG_BITS)) begin
m_current = get();
m_data = data;
m_be = byte_en;
m_is_read = is_read;
cg_bits.sample();
end
endfunction
endclass : register_a

---------------------------------------------------

Rgeister class snippet :
------------------------------------------------------
The register fields are being configured as below :
this.A1 = uvm_reg_field::type_id::create("A1");
this.A1.configure(this, 16, 0, "RW", 0, 16'hd, 1, 0, 1);
this.A2 = uvm_reg_field::type_id::create("A2");
this.A2.configure(this, 16, 16, "RW", 0, 16'hd, 1, 0, 1);

The reset values of the fields as mentioned above is
A1 = 16'hd & A1 = 16'hd.
-----------------------------------------------------------------

We are facing the following issues :
------------------------------------------------------------------------
Issue1 : After reset, if the register is accessed using the hierarchy :
..A1.value , the value read is always zero. While the expected value is 16'hd.

Issue 2 : Because of Issue 1 , we see that the coverage collected on the default value of the register is wrong.
In the coverpoint A1_value , bins "others" should have been hit because reset value of the register is 16'hd but always bins "min" is hit which is wrong.
---------------------------------------------------------------------------

Regards
Divya Dhiran

UVM SystemVerilog Basics in 24 short videos

Adam Sherilog — Thu, 10 May 2012 16:30:32 GMT

All,

Axel Scherer manages a team of UVM experts and has recorded their collected experience in a series of 24 UVM SystemVerilog basics videos. Each video is between 2 and 5 minutes making them easy to view when you have some free time, and easy to review when you're looking for a refresher.

The videos are open to all viewers with no registration required. Just a little Cadence EDA360 to help the UVM community.

http://www.youtube.com/playlist?list=PL7FE0CE1170C06FDE

The initial set of topics include the following and we expect to do more in the future:

Introducing UVM
Example DUT
UVM Environment
Interface UVC
Collector
Monitor
Sequence Item
Sequence
Driver
Sequencer
Agent
Agent types
Interface UVC environment
Virtual Sequencer - Sequence
Module UVC
Scoreboard
DUT Functional Coverage
Testbench
Test
Configuration
Factory
Phases
Objections
Virtual Interface

=Adam Sherilog
Cadence Verification Product Director

Sequencer Arbitration

tkramer — Thu, 10 May 2012 15:09:11 GMT

Hi,

Can anyone provide any information about the arbitration scheme used in uvm_sequencer_base? It appears that I am getting a deadlock between the sequence/driver handshaking, as start_item is never returning. I was looking through the code and it appears to be blocking in the m_wait_for_arbitration_completed method of uvm_sequencer_base, at
wait(lock_arb_size != m_lock_arb_size );
If anyone has any insight, I would really appreciate it

Thanks,
Tim

referencing an array of uvm_analysis_imp in a scoreboard

makers78 — Tue, 08 May 2012 22:08:12 GMT

I have been working with SV UVM for about 6 months now, over that time I've learned a combination of 1.0 and 1.1 so things are getting a bit confused. I am building a new scoreboard component working with new interface UVCs I created. I have a DUT with multiple identical interfaces which I want to feed into my scoreboard. I am trying to figure out how these uvm_analysis_imp classes are built and what I can access, in particular how I can access the index of a given handle. My thought is something like this:

class packet_scoreboard #(parameter NUM_IF=2) extends uvm_scoreboard;

`uvm_analysis_imp_decl(_pkt_in)

uvm_analysis_imp_pkt_in #( packet_in, packet_scoreboard ) pkt_in[NUM_IF-1:0];

...

function new ( string name = "packet_scoreboard" );
super.new(name);
for ( int i = 0; i < NUM_IF; i++ )
pkt_in[i] = new( $sformatf("pkt_in[%0d]", i), this);
endfunction

virtual function void write_pkt_in( packet_in pkt );
...
uvm_report_info( get_type_name(), $sformatf("Received packet on interface %0d", ???), UVM_DEBUG );
...
endfunction

endclass

Thanks,
Matt

register access

chenyong — Tue, 08 May 2012 09:18:44 GMT

Hi,

from UVM examples on codec, I found some code for register model access like this:

if (!regmodel.RxStatus.Align.get()) begin
regmodel.IntMask.set('h000);
regmodel.IntMask.SA.set('b1);
regmodel.IntMask.update(status);
...
end
...
regmodel.IntSrc.write(status, -1);
..

My questions are:
1) regmodel.IntMask.set('h000) has set the model to 000, why there is a code to set SA field to 'b1 followed? I guess it could be finished by regmodel.IntMask.set('h001), is my guess right?

2) suppose dut is different from register model for IntMask,
regmodel.IntMask.set('h00f);
regmodel.IntMask.update(status);
will write 'h00f to dut and update register model at the same time with same value, it this correct?

3) In code "regmodel.IntSrc.write(status, -1)", what does "-1" should be? from simulation (incisive/11.10.002) I found value 0x1ff is written to dut, why?

thanks

Verify shared address map with stand-alone and unified enable signals by RGM or REG?

leo_chen — Tue, 08 May 2012 07:52:45 GMT

There are 3 channels in my DUT, these 3 channels have the same register files, which have the same address map.
There are 4 CE (channel enable signal) on the interface, CE0, CE1, CE2 and CE_all.
There is only one address signal and one write data signal, like normal bus.

When a write transaction is initiated ...
If CE_all is asserted, the selected registers in all 3 channels are written.
If only CE0 is asserted, only the selected register in channel 0 is written.
If only CE1 is asserted, only the selected register in channel 1 is written.
If only CE2 is asserted, only the selected register in channel 2 is written.

The same address on the bus, but may have 4 different effects.

I am not sure if I can implement the register files for this specification by Cadence's RGM or UVM_REG?

The most challenging thing I can imagine so far is that CE_all need to update all register database.

Shared address map is also a problem, maybe using different register database can help, but contradict CE_all case.

Please kindly help.
Thanks.

separate logging verbosity for fileio and STDOUT

naveeng — Mon, 07 May 2012 22:50:16 GMT

Is there a way to specify accomplish a lower verbosity for messaging to STDOUT, and a higher verbosity for messaging to files?

Thanks a lot for your suggestions!

Error loading design during QuestaSim simulation of VHDL Design with SystemVerilog TB

pratyaksharn — Mon, 07 May 2012 13:35:17 GMT

Hello,

I am trying to create a UVM testbench on a VHDL Design.
I have created a make file to simulate the design with UVM testbench.
I am using Questasim 10.1 for the simulations.

The make file looks like this
"
vlib work
vcom -93 -f compile_source.f
vlog -f compile_tb.f
vsim -c +UVM_TESTNAME=rcc_base_test rccgpu badge_tb_top
"

When I run the command , I am able to compile VHDL, SystemVerilog Code.
However I get the following error during elaboration.

"
Top level modules:
badge_tb_top
/tools/mentor/questa_sim_10.1/questa_sim/linux/vsim -c +UVM_TESTNAME=rcc_base_test rccgpu badge_tb_top
Reading /tools/mentor/questa_sim_10.1/questa_sim/tcl/vsim/pref.tcl

# 10.1

# vsim +UVM_TESTNAME=rcc_base_test -c rccgpu badge_tb_top
# ** Note: (vsim-3812) Design is being optimized...
# // Questa Sim
# // Version 10.1 linux Dec 5 2011
# //
# // Copyright 1991-2011 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# //
# Loading std.standard
# Loading std.textio(body)
# Loading ieee.std_logic_1164(body)
# Loading ieee.std_logic_arith(body)
# Loading ieee.std_logic_unsigned(body)
# Loading work.badgefuncpkg(body)
# Loading work.badgepkg
# Loading ieee.numeric_std(body)
# Loading work.rccgpu(rtl)#1
# Loading sv_std.std
# Loading mtiUvm.uvm_pkg
# Loading work.mem_if_sv_unit(fast)
# Loading work.badge_tb_top(fast)
# Loading mtiUvm.questa_uvm_pkg(fast)
# ** Error: (vsim-3171) Could not find machine code for [COLOR="rgb(255, 140, 0)"]'/home/prra/trunk/badgeComponent/testbench/uvm_tb_rccgpu/work.rccgpu(rtl)'.
# Error loading design
Error loading design
make: *** [questa] Error 12[/COLOR]
"

I have also created a wrapper file in SystemVerilog and instantiated the wrapper in the top testbench file.
Please help.

IUS92 SV support:

shidb02 — Fri, 04 May 2012 04:12:45 GMT

Hello,
Does IUS92 support sv's process class?
Does IUS92 support template class using virtual class?

Is there any method to make IUS92 sim uvm1.1 ? I encounter lots of errors using ius92 and uvm1.1