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List of Contributions |
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Contributor: samarthkumar143
Date: February 3, 2012
Description: Enjoy your nights by talking online with beautiful and sexy indian girls on chat or on web. chat girls... more
Download: Water lilies.jpg
# of Downloads: 2
Simple UVM 1.1 UVC template generator - v1.10
Contributor: cdnmcgrath
Date: January 18, 2012
Description: Updated with a few bug fixes. Two minor new features added with v1.10: -use_seqr : by default, no sequencer component is created, this switch will force a custom uvm_sequencer component to be generated (not available with -one_file) -one_file : generate simple uvc in single... more
Download: juvb11.tar.gz
# of Downloads: 38
Cadence UVM_RGM2.7.5 release
Contributor: vishal.jain
Date: January 10, 2012
Description: UVM_RGM2.7.5 is the UVM version of the Cadence Register and Memory package that has been tested by multiple users on all major commercial simulators. Bug Fixed: Fixed issue with... more
Download: uvm_rgm_2.7.5.tar.gz
# of Downloads: 395
Linear PCM integrated example test bench 0.2
Contributor: petermonsson
Date: December 14, 2011
Description: A first cut at a simple integrated example test bench for people who want to learn UVM. This is pre-alpha, unreviewed and buggy code. If you use this as a basis for anything other than reviewing it for... more
Download: lpcm-0.2.tar.gz
# of Downloads: 78
UVM / OVM Harness Whitepaper 1.2
Contributor: DavidLarson
Date: December 7, 2011
Description: This update adds a section that addresses how to connect harnesses to arrays of sub-modules in a virtual harness. Harnesses are a proven methodology to hierarchically reuse interface connections from the block to the chip level.... more
Download: harness.1.2.tar.gz
# of Downloads: 92
Cadence UVM_RGM2.6.1 release
Contributor: vishal.jain
Date: November 29, 2011
Description: UVM_RGM2.6.1 is the UVM version of the Cadence Register and Memory package that has been tested by multiple users on all major commercial simulators. Bug Fixed: Fixed issue with syncing... more
Download: uvm_rgm_2.6.1.tar.gz
# of Downloads: 232
UVM ML
Contributor: EfratS
Date: November 9, 2011
Description: UVM-ML Version 1.1 (updated Nov-2011) Cadence has extended the UVM beyond SystemVerilog to also support e testbenches and SystemC models, including the ability to easily use verification components and... more
Download: uvm_ml_1.1.tar.gz
# of Downloads: 957
Multi-language example: SC reference model in UVM SV testbench
Contributor: phuynh
Date: October 19, 2011
Description: This example shows how to integrate a SystemC reference model into a UVM SystemVerilog testbench. The connections between SC-SV are done using TLM-1.0 and the multi-language library from Cadence.... more
Download: ml_example-yapp_router.tgz
# of Downloads: 150
UVM Integration with SystemC TLM2
Contributor: StuartSwan
Date: September 22, 2011
Description: This contribution contains a small, working example that demonstrates a general purpose, scalable approach for integrating UVM-SV and UVM-e models with SystemC TLM2 models. Please see the PACKAGE_README.txt file and the uvm_tlm2_integration.pdf slides within thekit for further information on... more
Download: uvm_tlm2_integration.tar
# of Downloads: 283
UVM 1.1 template generator - version 1.09
Contributor: cdnmcgrath
Date: September 16, 2011
Description: Version 1.09. Cleaned up version. Added a README. -h (-help) and -t (-template) made a tiny bit smarter. ... more
Download: juvb11.tar.gz
# of Downloads: 224
