By Nick Heaton – Cadence Incisive Verification Kit Architect
Yet another open-source donation … “big deal” you may be saying so why with this one should I sit up and take notice? The UVM Reference Flow is a ground-breaking move by Cadence which re-inforces the market push for a single vendor neutral verification reference methodology. By donating an Open-Source design in Verilog and testbenches in SystemVerilog, Cadence is delivering a major leg-up for the UVM eco-system. Not only will users have a realistic example to learn about UVM but they will also have a common database around which fertile discussions and technical exchanges can be based. Given the EDA Industry’s penchant for proprietary solutions and it’s desperate attempts to cling on to them through constant FUD, the sudden outbreak of sanity that Accellera has brought through the UVM push is truly a breath of fresh air. For the users an end to the “my methodology is bigger than yours” arguments can only be a massive positive and may finally hail the beginning of stability in advanced verification.
So what should you do now? Lets review the facts – the big deal is that we are at ground zero, a new beginning to set the world anew. If you have not done so already, register yourself immediately on the forums for this site. Download the UVM Reference Flow, get yourself up and going on UVM so you can take advantage of all its now benefits and values. Think about it for a second – when in the history of EDA has there been such an alignment around verification methodology ? – can we finally get to a spot where verification is NOT the #1 issue in SOC design ? Perhaps with serious push, standardization, and more contributions like this, we actually can, but I encourage you “the community” to get involved and help with the drive toward standardization. The big deal – you are finally getting what you wanted, so get on-board, you have nothing to lose and everything to gain.
For those “in the know”, this won’t be a surprise move from Cadence as their savvy customers have been using the Incisive Verification Kit for some 2 years. This hidden gem of a product is shipped free with the Incisive products, this UVM contribution is simply a subset of the Kit database. For those unfamiliar with the Kit it provides a wealth of workshops, labs, videos and documentation to help users to quickly ramp up on advanced verification methodology for both e and SystemVerilog.
This is yet the beginning of great things to come, stay tuned here, for UVM at its best.